1. Field of the Invention
The present invention relates to the photolithographic process used for manufacturing semiconductor devices. More specifically, the present invention relates to a method of manufacturing the reticles used in the photolithographic process for transcribing images onto layers stacked on a substrate.
2. Description of the Related Art
Photolithography is a process generally used to sequentially and selectively transcribe different pattern images, provided by a plurality of reticles, respectively, onto a wafer. More specifically, a photoresist on the wafer is exposed to light directed through the reticle, whereby the pattern image of the reticle is transferred to the photoresist. The photoresist is then developed so as to produce a pattern corresponding to the pattern image of the reticle. Subsequent processes, such as the etching of layers on the wafer and the deposition of conductive material on the wafer, are carried out using the patterned photoresist as a mask. The pattern image of a reticle thus provides the standard by which the subsequent processing of the wafer is carried out. The result of these processes is the forming of several conductive patterns throughout a plurality of layers on the wafer, which patterns are connected to collectively form a circuit pattern.
To produce a fine circuit it is thus important to manage the photolithographic process so that each pattern image is accurately aligned over the different patterns formed on the underlying layers. More specifically, a critical aspect of the photolithographic process is overlay management—the exact overlaying of a pattern image on a pre-existing patterned layer. Such an overlay is performed using alignment marks that are formed on the wafer and the reticle that is being used to expose the wafer.
Nowadays, many current attempts are being made to produce circuits having higher and higher and more accurate pattern densities through the designing of the pattern images of the reticles and/or the composition of the photoresist. A pattern image is formed, i.e., a reticle is typically produced, by laying out circuit pattern data on a quartz plate using a design instrument such as CAD (Computer Aided Design), by coating the quartz plate with a film of material such as chromium (Cr), and etching the film to form a pattern corresponding to the circuit pattern data. The circuit pattern data is generally classified into main chip circuit data 12 and reticle frame data 14, as shown in FIG. 1.
The main chip circuit data 12 is representative of the configuration of the image pattern to be formed at the central (image pattern) region of the reticle, and includes coordinate data 16. The coordinate data 16 represents the coordinates of the layout of the pattern image of the reticle 10.
The reticle frame data 14 is generated on the basis of the coordinate data 16. The reticle frame data 14 includes data representing the layout of alignment marks 20 that are to be provided in a scribe lane 18 of the reticle 10. Thus, the reticle frame data 14 represents the shape and size of the alignment marks 20 appropriate for the scribe lane 18. In this application, the term “alignment marks” is used to generically refer to all of the marks that may be found on the reticle 10, apart from the pattern image itself.
A conventional method of generating reticle frame data 14 will now be described with reference to FIG. 2. First, the pattern images are designed (ST102), namely all of the images to be transcribed onto the various layers on a wafer in manufacturing a particular product. The alignment marks are then selected (ST104). This step (ST104) comprises selecting appropriate alignments mark for each pattern image, and includes establishing the size and shape and reference coordinates of each alignment mark. The alignment marks also include data for correlating the reticle with the product that the reticle will be used to manufacture (e.g., an SRAM or a DRAM), and/or the layer of the product that the reticle will be used to expose. Such data may be realized as a bar code in the margin of the reticle 10.
Next, select ones of the alignment marks are discriminated as a “process mark” (ST106). The process mark comprises those alignment marks 20 that will be located in the scribe lane 18 of the reticle.
Once the process mark is established, the dimensions of the scribe lane region 18 are established based on the layout of the process mark and on the size of the pattern image (ST108).
The process marks for the respective pattern images are then laid out in the scribe lanes 18, for example (ST110). As shown in FIG. 3, this step of laying out a process mark is executed by confirming the location of the mark one by one against a plurality of marks (represented by Cells A, B and C in the figure), and by forming the process mark at that location using layout editing software (ST112). In this process, the reference coordinates are input to the software by a software technician.
However, there may be hundreds or thousands of reference coordinates of the pattern images. Thus, inputting the reference coordinates of a pattern image one by one to lay out the process marks in the scribe lanes 18 of the reticles requires a great amount of time.
Furthermore, the process mark on the reticle frame of each reticle is manufactured manually by a technician using layout editing software. Not only is this process time-consuming, but the accuracy and a reliability of this process is prone to errors made by the technician. Thus, even more time is spent re-checking the procedure and correcting it when necessary.